The present invention relates generally to mixer circuits, and in particular to a mixer circuit which can operate in either a bypass mode or mixing mode while retaining a high level of even order mixer product suppression.
Communication systems which transmit and receive signals often employ one or more mixing circuits to translate signals at a one frequency to another frequency. As known to the practitioner, the mixing circuits usually include two input ports for receiving two signals, typically identified as RF and LO signals, and an output port for providing a signal at the mixing product of the two input signals. As is well known, the mixing product of the two signals, typically referred to as the IF signal, may be expressed as:IF=|MfRF±NfLO|
As can be seen, signals at multiple frequencies are produced during the mixing process, one of which is most often desired, e.g., a downconverted signal at frequency RF-LO. The presence of remaining signals at frequencies within the operational band of the mixer's output, conventionally referred to as “interferers,” can be problematic, as they can interfere with the proper operation of the communication system. Accordingly, the elimination of unwanted interferers is an important design criterion in most systems.
Several mixer architectures are known in the art as providing rejection of at least some of the potentially interfering signals. For example, doubly balanced mixers are known in the art as providing excellent rejection of even order mixing products, a characteristic which makes the architecture ideal in a variety of communication systems.
FIG. 1A illustrates a simplified switch diagram of a doubly balanced mixer as known in the art. The mixer 100 includes RF and IF ports 110 and 130, respectively, each of which is shown differentially, but may be single-ended in another embodiment. The differential RF signal 110 is supplied to the input of SPDT switches 122, the states of which are switched at a rate determined by an LO signal 125 supplied thereto. The outputs of the switches 122 are coupled to differential IF ports 130 operable to provide the differential IF signal 130.
FIG. 1B illustrates the doubly balanced mixer of FIG. 1A as a Gilbert cell multiplier or mixer circuit known in the art. The mixer circuit includes two cross-coupled differential transistor pairs 122 whose base terminals are coupled to the LO source 125, collector terminals are coupled to the IF loads 130, and emitter terminals are coupled to buffer transistors 117. Responsive to the differential RF signal applied at terminals 110a and 110b, a voltage difference is established across resistor 115, resulting in the corresponding modulation of the quiescently-supplied current driving the transistor pairs 122 that comprise the mixer core. Those skilled in the art will appreciate that illustrated mixer circuit is only exemplary, and numerous variations of the circuit are also widely used.
While doubly balanced mixers provide a high level of even order mixing product suppression, circuit imperfections lead to degradation in that suppression. For example, a relatively low impedance parasitic 112 (e.g., capacitance) can load the emitter nodes of the mixers, the impedance operating to convert the rectified LO voltage into a common mode even order LO interferer current. The LO interferer can then pass through the mixer core and to the output loads.
Reduced mixer even-order suppression can be especially problematic when the mixer is integrated with other circuitry. FIG. 2 illustrates one example of such an instance where multiple mixers are supplied by a single VCO. Each mixer is configured to operate in either a mixing mode, whereby the synthesized signal 205 and input signals 210a and 210b are provided to respective mixers 220a and 220b to produce respective mixed signals 230a and 230b, or in a bypass mode, whereby the synthesized signal 205 is not supplied to the mixer 220c and the input signal 210c is routed such that it bypasses the mixer 220c. 
In such a system, the LO even order mixer interferers can couple to the VCO via substrate leakage, indirect conductor leakage (ground, power or logic lines), magnetic or electrostatic coupling, or other such means. Within the VCO, the even order interferers may cause spurs in the VCO output, or may combine with odd order harmonics of the desired signal to produce an interfering signal at the desired frequency of oscillation. In the latter case, the interfering signal will produce a phase offset in the VCO-generated output. If that coupling should change, a phase step will be introduced into the system which the PLL will attempt to correct for. If the phase step is large enough, the consequence can be a disruption of the digital demodulation process.
What is therefore needed is a new mixer circuit operable in either a bypass mode or mixing mode, and which can maintain a substantially constant level of LO even order interference independent of its operation in either the bypass or mixing mode.